FPGA UART | Suman

The objective of this project is to be able to understand the UART protocol and write a verilog code for this communication and implement the design on an FPGA board.

Tools used:

1.Quartus prime

2.Verilog HDL

3.DE2 115 FPGA(cyclone IV E)

UART is communication protocol that uses no clock and hence is known as asynchronous.A high to low indicates the start of a frame and then every once a time period, the bit is received and after 8 bits transmitted again a high to Low transition takes place indicating the arrival of the next frame and so on. For further details regarding the protocol, you can check the documentation below:

UART documentation